1Technical Field
The invention relates to multi-port dynamic random access memory (or DRAM) chips, and more particularly to a multiplexed serial architecture for a video DRAM (or VRAM).
2Background Art
In concert with the general trend in the DRAM industry directed to doubling the density of memory chips every two - three years, the applications of DRAMs have been extended from the conventional random (or parallel) access mode to a serial access mode. In the parallel access mode, a given word line is selected in each memory array, and a given bit line (or bit line pair, in the case of the folded bit line arrangement shown e.g. in U.S. Pat. No. RE 32,708 to Hitachi) within the array is selected, such that the same memory location in all of the arrays is available for either reading or writing at the same time. In a serial access mode, after a given word line is accessed, a plurality of bit lines coupled to the word line are addressed, and the respective bits of information are read out in a serial fashion.
During the 1980s the general idea of a single DRAM having both serial and parallel access capabilities first appeared. In such arrangements, the chip has two output ports--one serial, one parallel. The serial port interfaces with a plurality of latches connected up to form a shift register latch (SRL), and the parallel port is coupled to the data lines as in a conventional DRAM. See e.g. U.S. Pat. No 4,541,075 (issued to Dill et al. and assigned to IBM); see also U.S. Pat No. 4,639,890, U.S. Pat. No. 4,648,077, and U.S. Pat. No. 4,683,555 (all assigned to Texas Instruments), and an article by Ishimoto et al entitled "A 256K Dual Port Memory," International Solid State Circuits Conference, Digest of Technical Papers, February 1985, p. 38-39.
In the dual-port arrangements disclosed in the above references, each array of memory cells has its own plurality of sense amplifiers and shift register latches. Another example of such an arrangement is shown in an article by Matick et al, entitled "All Points Addressable Raster Display Memory," IBM Journal of Research and Development, Vol. 28, No. 4, July 1984, pp. 379-392). In this paper, the two memory cell "islands" shown in FIG. 5 are two subarrays that share common sense amplifiers (the two subarrays are not independent arrays, because they depend on the same set of sense amplifiers to provide sensing. If two independent arrays shared the same sense amps, the cycle time of the memory would be doubled). Note that the sense amplifier is separated from the shift register array by a portion of the memory array.
In the general DRAM art, multiplexing schemes have appeared that enable one functional block to carry out a multiplicity of related operations. Examples of multiplexing in the DRAM art include U.S. Pat. No. 4,680,738 (issued to Tam and assigned to AMD--one of two shift register chains of a dual-port DRAM receive muxed address selection inputs in order to selectively bypass a multiplexed output operation); U.S. Pat. No. 4,773,048 (issued to Ogawa and assigned to Fujitsu--the bit line inputs/outputs are muxed between the serial and parallel ports, to enable parallel data transfers), and U.S. Pat. No. 4,754,433 (issued to Chin et al. and assigned to IBM--the bit lines of a conventional DRAM are muxed onto I/O lines, which in turn are muxed onto data lines).
In the dual-port DRAM art, the use of a separate shift register for every independent array takes up a large amount of chip real estate. Thus, there is a need in the art to reduce the number of shift register latches as much as possible, without sacrificing operating modes or performance (i.e., access speed).